#include "mmu.h"
#include "ft_types.h"
#include "sdkconfig.h"
#include "parameters.h"

#ifdef CONFIG_TARGET_ARMV8_AARCH64


const struct arm_mmu_region mmu_regions[] = {
    MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
                          0X00, 0x40000000,
                          MT_DEVICE_nGnRE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION",
                          0x40000000, 0x10000000,
                          MT_DEVICE_nGnRnE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("PCIE_REGION",
                          0x50000000, 0x30000000,
                          MT_DEVICE_nGnRE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("DDR_REGION",
                          0x80000000, 0x80000000,
                          MT_NORMAL | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("PCIE_REGION",
                          0X1000000000, 0X1000000000,
                          MT_DEVICE_nGnRE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("DDR_REGION",
                          0X2000000000, 0X2000000000,
                          MT_NORMAL | MT_RW | MT_NS),
};

const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions);

const struct arm_mmu_config mmu_config = {
    .num_regions = mmu_regions_size,
    .mmu_regions = mmu_regions,
};

#else

#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)

struct mem_desc platform_mem_desc[] = {
    {0x80000000,
     0x80000000 + 0x7f000000,
     0x80000000,
     DDR_MEM},
    {0, //< QSPI
     0x1FFFFFFF,
     0,
     DEVICE_MEM},
    {0x20000000, //<! LPC
     0x27FFFFFF,
     0x20000000,
     DEVICE_MEM},
    {FT_DEV_BASE_ADDR, //<! Device register
     FT_DEV_END_ADDR,
     FT_DEV_BASE_ADDR,
     DEVICE_MEM},
    {0x30000000, //<! debug
     0x39FFFFFF,
     0x30000000,
     DEVICE_MEM},
    {0x3A000000, //<! Internal register space in the on-chip network
     0x3AFFFFFF,
     0x3A000000,
     DEVICE_MEM},
    {FT_PCI_CONFIG_BASEADDR,
     FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
     FT_PCI_CONFIG_BASEADDR,
     DEVICE_MEM},
    {FT_PCI_IO_CONFIG_BASEADDR,
     FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
     FT_PCI_IO_CONFIG_BASEADDR,
     DEVICE_MEM},
    {FT_PCI_MEM32_BASEADDR,
     FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
     FT_PCI_MEM32_BASEADDR,
     DEVICE_MEM}};

const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);




#endif


u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
    if (*cpu_mask == 0)
    {
        return 0;
    }

    *target_list = 0;
    *cluster_id = 0;

    if (*cpu_mask & 0x3)
    {
        if ((*cpu_mask & 0x3) == 0x3)
        {
            *target_list = 3;
        }
        else if ((*cpu_mask & 0x1))
        {
            *target_list = 1;
        }
        else
        {
            *target_list = 2;
        }
        *cpu_mask &= ~0x3;
    }
    else if (*cpu_mask & 0xc)
    {
        *cluster_id = 0x100;
        if ((*cpu_mask & 0xc) == 0xc)
        {
            *target_list = 3;
        }
        else if ((*cpu_mask & 0x4))
        {
            *target_list = 1;
        }
        else
        {
            *target_list = 2;
        }
        *cpu_mask &= ~0xc;
    }
    else
    {
        *cpu_mask = 0;
        return 0;
    }

    return 1;

}

u64 GetMainCpuAffval(void)
{
    return 0;
}
